Burst random access memory employing sequenced banks of local tri-state drivers
US5617555A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Nov 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A burst dynamic random access memory (DRAM) (10) is disclosed having memory cells arranged in a number of quadrants (22), each quadrant including local I/O lines (24) for accessing the memory cells therein. The local I/O lines (24) of each quadrant are commonly coupled to global I/O lines (26) by tri-state driver banks (30). According to a row address and a first portion of a column address, a row decoding circuit (36) and column decoding circuit (40) couple one set of local I/O lines (24) within each quadrant (22) to selected columns within the quadrants (22). A bank sequencer (48) receives a second portion of the column address and generates burst sequence of different bank select signals. Each bank select signal enables a different set of tri-state driver banks (30). The enabled tri-state driver banks (30) provide a data path between the local I/O lines (24) and the global I/O lines. By enabling a different combination of tri-state driver banks (30) for each bank select signal, burst access is provided to the burst DRAM (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.