Modular chip select control circuit and method for performing pipelined memory accesses
US5617559A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1994 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Aug 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modular chip select control circuit (80) is scalable by having an address decode stage (90) with a first number of address decoders, a control stage (100) with a second number of control units, and a pin configuration stage (110) with a third number of pin configuration logic circuits. These three numbers, defining the number of memory regions, the access pipeline depth, and the number of chip select signals, respectively, are independent and may be changed between chip designs to accommodate different system needs. The control stage includes an early pipeline control circuit (186) which allows the control units (170, 180) to pipeline pending memory cycles, based on an accessed region's characteristics. The early pipeline control circuit (186) together with the control units (170, 180) enforce a set of pipelining rules to ensure data integrity and proper cycle termination, thus providing an efficient series of pipelined memory access cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.