Method of slowing down code execution in a microprocessor including an internal cache memory
US5617576A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Feb 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution speed controller for controlling the effective processing rate of a microprocessor including an internal cache memory. In one embodiment, the execution speed controller monitors the activities of the microprocessor to determine when it is executing a section of code whose execution should be slowed. When such a determination is made, the execution speed controller periodically asserts at least one control input to the microprocessor. This periodically prevents the microprocessor from accessing the main memory and the internal cache memory, thereby slowing microprocessor execution. In this embodiment, only those software applications requiring slow down are effected. Newer software applications may not require this mode and may run at full speed. An alternate embodiment that does not require a triggering event is also described. In this embodiment, execution of all software applications is slowed down. This is referred to as the "compatibility" mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.