Narrow lateral dimensioned microelectronic structures and method of forming the same
US5618383A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1994 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Mar 30, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, there is provided a method by which narrow lateral dimensioned microelectronic structures can be formed using low temperature processes. An uncured resist layer (e.g. PMMA 42) is deposited on a supporting layer (e.g. silicon 40) and patterned. Then, by using an isotropic process such as a low temperature chemical vapor deposition, a conformal layer (e.g. silicon oxynitride 44) is deposited substantially evenly on the vertical walls and on the horizontal surfaces of the uncured resist layer. An anisotropic etch such as reactive ion etching is then used to substantially remove the conformal layer from the horizontal surfaces without substantially etching the conformal layer from the vertical walls of the resist. The resist can then be selectively removed, producing isolated vertical sidewall structures (e.g. silicon oxynitride 46) which could be used, for example, as a negative tone mask. Alternatively, instead of removing the resist, another resist layer (e.g. PMMA 48) could be spun on to planarize the structure, and then etched back to reveal the sidewall structures. The sidewall structures could then be selectively etched, producing a resi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.