Manufacturing method and apparatus of a semiconductor integrated circuit device
US5618744A · kind A · utility
110Cited by
3References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 22, 1993 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Sep 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.