Method of forming a semiconductor device having a capacitor and a resistor
US5618749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/136
Abstract
A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor is monolithically manufactured. Polycrystalline silicon film, a dielectric film, and another polycrystalline silicon film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as an etching protection mask for the resistor and a capacitor. A refractory metal silicide for a polycide gate is uniformly deposited over the remaining another polycrystalline silicon films and dielectric films. The refractory metal silicide and polycrystalline silicon are consecutively etched through a patterned resist mask and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a capacitor having small change in capacitance versus applied voltage is manufactured in a MOS IC device having a polycide gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.