Semiconductor memory device with a plurality of bonding pads arranged in an array
US5619472A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory comprising core blocks 1, 2, 3 and 4 each comprising memory cell arrays each having a plurality of memory cells in a matrix and sense amplifiers and decoders accompanying the memory cell arrays. An inter-block region is arranged among the core blocks wherein data signal lines, address signal lines and control signal lines are provided. Pad arrays IO Pad and A Pad each comprising a plurality of pads and buses IO Bus and A Bus are arranged among the core blocks. The buses A Bus are jogged in a connection region. The buses IO Bus and A Bus are arranged successively in the inter-block region and the data signal lines, the address signal lines and the control signal lines are connected to the buses A Bus and IO Bus in the inter-block region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.