Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US5619506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/073
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A jitter/wander reduction mechanism monitors the ratio of pulse stuffing, to detect whenever the pulse stuffing ratio is proximate a prescribed undesirable ratio of stuffs per stuffing opportunity, which causes the wander to be a large number of unit intervals. A stuffing pulse accumulator-controlled frequency shift control circuit monitors the signal produced by a multiplexer (and demultiplexer for full duplex mode) control logic circuit and incrementally adjusts, as necessary, the frequency of a synchronized clock signal input to the multiplexer (and demultiplexer). The magnitude of the incremental frequency shift is sufficient to drive the synchronized clock away from the frequency associated with the undesired stuff ratio to a frequency that is sufficiently separated from the undesired value to produce a stuffing ratio other than the undesired value and reduce the jitter/wander.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.