Delayed FIFO status for serial shift emulation
US5619681A · kind A · utility
22Cited by
15References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1993 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Jun 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.