Method for fabricating highly conductive vias
US5619791A · kind A · utility
97Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The thickness uniformity of a plated metal layer inside a via hole can be enhanced by intersecting a conductive via with an insulating aperture before plating. The new via configuration improves the mass transfer of the plating. It is believed that the apertures lower the local solution ohmic resistance near the via holes. The method can be applied to the manufacture of a wide variety of circuit boards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.