Method of manufacturing a semiconductor memory device having a capacitor
US5620917A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1996 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Mar 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
In a semiconductor memory device having a novel structure of a wiring layer and a large capacitance capacitor and the manufacturing method therefor, on the transistor formed on the semiconductor substrate, a first conductive layer is formed extending along with the gate electrode of the transistor and connecting with the gate electrode, a storage electrode of a capacitor is formed on the first conductive layer by interposing the insulation film between the first conductive layer and the source region of the transistor, and a second conductive layer is formed in connection with the first conductive layer at a portion between memory cell array and the peripheral circuit region. Storage electrodes can be made thicker without affecting to the step-difference between memory cells and the peripheral circuit region, so that a more reliable semiconductor memory device with a capacitor having a larger capacitance can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.