Field emission device with over-etched gate dielectric
US5621272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | May 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2329/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by an insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays of microtips (14) are located in mesh spacings (16), within apertures (26) formed in extraction electrode (22) and subcavities (141) formed through apertures (26) in insulating spacer (125). Subcavities (141a) are open to row-adjacent and column-adjacent subcavities (141b, 141c) to form larger main cavities (144). Posts (143) of insulating spacer (125) separate diagonally-adjacent cavities (141d). Subcavities (141) are formed by over-etching a layer of insulating spacer material (25) through apertures (26) before or after forming microtips (14) through the same apertures (26). Over-etching reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.