Amplifier having a reduced distortion rate
US5621356A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Dec 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45722
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier including a first output transistor (T2a) and a second output transistor (T3a) having the same polarity and arranged in push-pull configuration, and an input transistor (T1a) whose collector is coupled to the base of the first output transistor (T2a). The amplifier also includes a third output transistor (T2b) and a fourth output transistor (T3b) which are also arranged in push-pull configuration, and a supplementary input transistor (T11b) whose emitter is coupled to the emitter of the input transistor (T1a) and whose collector is coupled to the base of the second output transistor (T3a) and to the base of the third output transistor (T2b), the base of the fourth output transistor (T3b) being coupled to the collector of the input transistor (T1a).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.