Voltage supply isolation buffer
US5621360A · kind A · utility
13Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Aug 2, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.