Delta sigma analog-to-digital converter with temporally interleaved architecture
US5621408A · kind A · utility
19Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Feb 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/456
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delta sigma converter according to the present invention replaces the quantizer of a conventional delta sigma converter, such as a comparator followed by a latch, with N quantizers, each operating at a reduced frequency f.sub.s /N and phase offset from each other by 2.pi./N. The quantized outputs are assembled in accordance with a control signal to produce a feedback signal at a frequency f.sub.s and the feedback signal is applied to a subtractor of the delta sigma converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.