Polarity selection circuit for bi-phase stable FPLL
US5621483A · kind A · utility
6Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Jul 10, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/22
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A television receiver includes a synchronous demodulator including a bi-phase stable PLL for controlling sampling of the received signal to produce data. A phase inverter reverses the phase of the data in response to a control signal. Data segment sync characters are recovered with a sync correlation filter that also yields a sign bit indicating polarity. If the sign bit is wrong for a predetermined number of data segment sync characters, a control signal is produced to operate the phase inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.