Nonvolatile memory blocking architecture and redundancy
US5621690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory includes a global line. A plurality of memory blocks and a redundant block are also included in the memory, each block having a plurality of local lines and a decoder for selectively connecting the global line to one of the local lines when the decoder is enabled and for isolating the local lines from the global line when the decoder is disabled. When one of the plurality of blocks is found to be a defective block, the defective block is replaced by the redundant block. Circuitry is provided for disabling the decoder of the defective block and enabling the decoder of the redundant block whenever the defective block is addressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.