Data signal distribution circuit for synchronous memory device
US5621698A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Dec 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data signal distribution circuit for a synchronous memory device comprising a data generation source for generating successive data signals in response to an external clock signal. The data signal distribution circuit comprises at least two control switches for switching the data signals from the data generation source to at least two peripheral circuits, a strobe signal generator for delaying the external clock signal by a propagation delay time of the data generation source and generating a strobe signal in response to the delayed external clock signal, and an internal address generator for generating an internal address signal in response to the strobe signal from the strobe signal generator and supplying the generated internal address signal to the control switches. The strobe signal has a predetermined logic level for a predetermined duration beginning with a pulse edge of the delayed external clock signal. The internal address signal has at least two bits, only one of which has the predetermined logic level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.