CMOS technology high speed digital signal transceiver
US5621755A · kind A · utility
17Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1994 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Oct 28, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed digital signal transceiver in CMOS technology, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.