Integrated semiconductor circuit or micromechanical component and process therefore

US5623164A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Stephan Auer · Dachau, DE
• Armin Kohlhase · Neubiberg, DE
• Hanno Melzner · Sauerlach, DE

Key dates

• Filing date: May 10, 1995
• Grant date: Apr 22, 1997
• Expiry date: May 10, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31053
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

For the global planarization of a semiconductor circuit or a micromechanical component with a step between a higher-lying region and a lower-lying region, the regions being large in area, it is envisaged to deposit a first layer (50), remove it again in the higher-lying region apart from a rib (50), deposit a second layer (51) and then, in a CMP step, planarize the entire arrangement.