Offset reduction in a zero-detect circuit
US5623220A · kind A · utility
11Cited by
27References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1994 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Sep 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/81
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.