Compressed-domain bit rate reduction system
US5623312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1994 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Dec 22, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/6137
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Improved bit rate reduction techniques are disclosed. When incorporated into an existing video processing system having a DCT coefficients processor, the motion vector processor disclosed herein provides enhanced computational and memory storage efficiencies over prior art designs. The motion vector processor includes a microprocessor and associated motion vector memory. The motion vector memory is adapted to store a plurality of motion vectors corresponding to at least one image frame containing a plurality of macro blocks. Each motion vector is represented by an X value and a Y value, the X value and the Y value signifying image changes within a given macro block from a given frame to the immediately preceding frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.