Memory cells and memory devices with a storage capacitor of parasitic capacitance and information storing method using the same
US5623442A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1995 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Jan 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object of the present invention is to provide a DRAM of a special form, a non-volatile memory cell incorporating the DRAM, and a semiconductor device which incorporates a DRAM structure and a non-volatile memory cell and where data can be written and erased with high accuracy. The semiconductor memory device has a sub bit line BLs1 to which the main bit line BL1 is connected via a selector transistor Tr1, and non-volatile memory cells M1-Nn, i.e., memory transistors whose drain electrodes are connected to the sub bit line Bls1. An a-c pulse generator applies an a-c voltage to the control gates of the non-volatile memory cells M1-Nn. The DRAM cell is formed of a capacitor element formed of parasitic capacitance of the sub bit line BLs1 and the drain electrodes of the non-volatile memory cells connected to the bit line BLs1. An arbitrary non-volatile memory cell Mk is connected with the memory node N of a DRAM cell, thereby implementing a non-volatile memory cell or non-volatile memory device having DRAM functions. The DRAM cells may operate independently of the non-volatile memory cells. Data is temporarily stored in the DRAM cell and is then transferred to the non-volatile memor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.