Logical cache memory for multi-processor system
US5623626A · kind A · utility
14Cited by
14References
3Claims
0Family size
Assignee
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Key dates
| Filing date | May 15, 1995 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | May 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical address, access is made to the logical tag to detect the existence of data, and when access is made using a physical address, access is made to the physical tag using an offset portion which does not depend on address conversion, to detect the existence of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.