Apparatus and method for reducing power consumption in a computer system
US5623677A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 1996 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Feb 29, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing the power consumption of a processor in a computer system where a programming structure running on the processor determines when the processor is in an inactive state to cause clocking signals and the power supply to be disabled to the processor. The processor is again coupled to the power supply and the clock signals in response to a periodic interrupt signal, a non-periodic interrupt or a bus request from a peripheral device. Thereafter, the programming structure signals the control logic again when the processor reenters the inactive state, such that the control logic disables the clock signals and decouples the power supply to the processor when the processor returns to the inactive state. The method is extended to offer the ability to shut down the processor from programming structures running on alternate masters or subsystem controllers within the same system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.