Reset configuration in a data processing system and method therefor
US5623687A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1995 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Jun 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/177
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data processor (10) configures internal circuitry during execution of a reset operation in response a logic state of a Mode Select signal. If an external bus control (44) determines the Mode Select signal is in a first logic state, configuration data is provided from a mask register (40). The data is transferred to a plurality of configuration registers (50) and, subsequently, to a remaining portion of data processor (10). If the Mode Select signal is in a second logic state, configuration data is provided from a plurality of bus terminals (48). The data is transferred to the plurality of configuration registers (50). The contents of the plurality of configuration registers (50) are transferred to bus interface unit (42) which subsequently transfers the data to a remaining portion of data processor (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.