Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension
US5623697A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1994 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Nov 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system having an industry standard architecture (ISA) bus with a 24-bit memory addressing capacity and a peripheral controller interconnect (PCI) bus with a 32-bit memory addressing capacity, is provided with a bridge coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) controller circuit that generates 32-bit memory addresses for DMA transfer operations over the PCI bus. The DMA controller circuit includes a pair of cascaded DMA controllers that generate the 16 least significant bits of the 32-bit memory addresses, and address extension logic having a low page register that provides the 8 next most significant bits of the 32-bit memory addresses, and a high page register that provides the 8 most significant bits of the 32-bit memory addresses. The 16 bits provided by the low and high page registers are concatenated with the lower 16 bits to form the 32-bit addresses. The DMA controller circuit is also provided with count extension logic that increases the transfer count from a 16-bit number to a 24-bit number, so that larger segments of memory may be moved in the individual DMA transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.