Memory interconnect network having separate routing networks for inputs and outputs using switches with FIFO queues and message steering bits
US5623698A · kind A · utility
86Cited by
16References
23Claims
0Family size
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Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17393
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor to memory interconnect network can be used to construct both small and large scale multiprocessing systems. The interconnect network includes network modules and memory modules. The network and memory modules are constructed of a series of n.times.m switches, each of which route n inputs to m outputs. The switches are designed such that message contention in the interconnect network is reduced. The switches, and thus the memory and network modules are highly modular, thus allowing virtually any scale multiprocessing system to be constructed utilizing the same components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.