Method of making low capacitance field emission device
US5624872A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1996 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Apr 8, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J9/025
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A process is described for manufacturing a field emission device that has low capacitance as well as low internal resistance. The process begins with the provision of an insulating substrate on which cathode columns and orthonal gate lines, separated by a relatively thick insulating layer (to reduce capacitance), have been formed. Openings in the gate lines, located above the cathode columns and extending down to the level of the insulating layer, are then formed. Using the gate lines as a mask, the insulating layer is then etched down to the level of the cathode columns, thereby forming wells in the insulating layer. These wells are then filled with additional conductive material which is then partially removed. This results in the formation of conductive pedestals, inside the wells, on which the microtips (which are then formed in the usual manner) rest. This allows the microtips to retain electrical contact with the cathode columns while still keeping their apexes in line with the gate line openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.