MOS transistor having a composite gate electrode and method of fabrication
US5625217A · kind A · utility
128Cited by
3References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 2, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Feb 2, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.