Semiconductor assembly for a three-dimensional integrated circuit package
US5625221A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Jan 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package assembly includes recessed edge portions extending along at least one edge portion of the assembly and an upper surface of leads being exposed therefrom, a top recess portion disposed on a top surface of the assembly, and a bottom recess portion disposed on a bottom surface of the assembly. When the assemblies are used in fabricating a three-dimensional integrated circuit module, the recessed edge portions accommodates leads belonging to an upper semiconductor assembly to achieve electrical interconnection therebetween, the top recess portion and the bottom recess portion belonging to an upper semiconductor assembly form a space to accommodate a heat sink or a capacitor plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.