Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium
US5625234A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 18, 1994 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Aug 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select line YS is arranged at a position where it uniformly spans over both members of a bit line pair which extend straight in parallel to each other without the twist part TW within an area of four bit line pairs (eight bit lines or auxiliary bit lines) that are simultaneously sensed. Within an area of the first set of bit line pairs (BL0,BL0-)-(BL3,BL3-), in addition to the bit line pair (BL1,BL1-), the line pairs (BL0,BL0-) and (BL2,BL2-) with the twist part TW are substantially capacitance-coupled with the Y select line YS0. In these bit line pairs, the parasitic capacitance for the Y select line YS0 is at equilibrium between a bit line and an auxiliary bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.