Flexible FPGA input/output architecture
US5625301A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | May 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buffer data conductors and output buffer enable conductors extending in either the row or the column direction, different ones of the output buffer data conductors and output buf…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.