Multiplexer having a plurality of internal data paths that operate at different speeds
US5625303A · kind A · utility
27Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Sep 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.