Two input-two output differential latch circuit
US5625308A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Nov 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.