Tuning method for integrated continuous-time filters
US5625317A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 1994 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Aug 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2210/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-frequency integrated continuous-time filter with built-in test mode. The present invention provides the ability to easily track the cutoff frequency of the filter without the additional power and area requirements and noise sources present in prior art master/slave tuning schemes. Furthermore, the filter being tested is the actual filter that is used to process signals, unlike the prior art where a similar but separate filter or oscillator is used to tune the bias values for both circuits. Better tuning accuracy is thus obtained in the present invention. The circuit is designed to oscillate in test mode at the cutoff frequency of the filter. Oscillation is achieved by moving the poles of the filter from the left half-plane either onto the imaginary axis or into the right half-plane. The filter frequency accuracy is established by trimming the frequency of the oscillation in test mode during wafer probe or by adjusting the circuit biasing to tune the cutoff frequency in test mode during power-up or between reads in a memory system. The oscillation is disabled during normal operation of the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.