System and method for phase lock loop gain stabilization
US5625325A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Dec 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The system and method for phase lock loop (PLL) gain stabilization uses a digital compensation technique to correct for the large amount of gain variation present in a voltage controlled oscillator (VCO) utilizing a varactor diode. AVCO is arranged with additional capacitance in parallel with the vatactor diode of the VCO. By using multiple capacitors, more or less capacitance can be switched into parallel with the vatactor diode. Gain variation is accomplished by switching capacitors into the circuit, and for each combination of capacitors used in the resonant inductance-capacitance (LC) circuit of the VCO, the gain of the phase detector in the PLL is adjusted simultaneously. The phase detector has a charge pump that drives a current into a loop filter having a capacitor with a fixed value. The gain adjustment is accomplished by varying the amount of current available from the charge pump to this filter capacitor. The gain compensation circuit that generates this charge pump current takes the same digital code used to control the capacitors in the VCO as an input and performs a digital-to-analog conversion in current mode. The analog current is then transformed into a second-order…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.