Apparatus and method for optimizing address calculations
US5625582A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Mar 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device performing arithmetic operations on a plurality of digital inputs to produce an effective address and a linear address in a single operation. The integrated circuit device comprises a first circuit, a first adder circuit and a second adder circuit. The first circuit performs logical operations on the plurality of digital inputs to produce a first group of output signals and a second group of output signals. The first adder circuit, coupled to the first circuit, performs a first set of arithmetic operations on the first group of output signals to produce an effective address. Concurrently, the second adder circuit, coupled to the first circuit and in parallel with the second adder circuit, performs a second set of arithmetic operations on the second group of output signals to produce a linear address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.