Timing recovery controller and method for adjusting the timing of synchronizing windows in a PSK demodulator
US5625652A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates. The unique word detector receives an input of binary data from the data decoder and using a correlation technique identifies one set of windows which substantially maximizes synchronization of the demodulator with the received PSK signal. After the synchronizing window has been identified the automatic frequency controller monitors any frequency drift of the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.