Information processing apparatus having dual buffers for transmitting debug data to an external debug unit
US5625785A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1995 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Jan 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus has an instruction execution unit (IEU), a counter, first and second FIFO buffers, and a selector. The IEU executes instructions. The counter traces an order of execution of the instructions executed by the IEU and stores the order of execution as an order data. The first FIFO buffer stores a branch source address data obtained by a branch instruction together with the order data. The second FIFO buffer stores a content of a memory obtained by a memory access instruction or push data obtained by a stack push instruction together with the order data. The selector selects one of the data stored in the first and second FIFO buffers and provides it to an external device. The selector selects the first FIFO buffer prior to the second FIFO buffer as long as the first FIFO buffer has the branch source address data stored therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.