Method and apparatus for concurrently accessing multiple memories with different timing requirements
US5625796A · kind A · utility
34Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system in which a plurality of processors or other memory access devices operate either synchronously or asynchronously with a memory interface device, which in turn provides access to one or more memory units on a time-division basis. This is accomplished by providing each memory unit a series of time-divisioned access opportunities and controlling the phase relationship between these time-divisioned access opportunities. Accordingly, two or more access devices can address an equal number of memory units simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.