Pulse generation circuit and memory circuit including same
US5627796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1996 |
| Grant date | May 6, 1997 |
| Priority date | — |
| Expiry date | Feb 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse generation circuit of a memory comprises a first logic operation unit for performing a logical operation on an address transition detection pulse and a delayed address transition detection pulse to produce first and second pulses, a switching unit controlled by an externally applied write enable signal for selecting one of the first and second pulses as an output pulse and for inverting the write enable signal, and a second logic operation unit for performing a logical operation on the output pulse and the inverted write enable signal from the switching unit to generate a word line enable signal and a sense amplifying enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.