Data transfer apparatus which allows data to be transferred between data devices without accessing a shared memory
US5627968A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 1994 |
| Grant date | May 6, 1997 |
| Priority date | — |
| Expiry date | Jul 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer apparatus which includes data devices which access a common, shared memory. Each data device is connected to a corresponding data buffer. A memory bus is connected to each of the data buffers and to the shared memory to allow data to be transferred between the data buffers and between the data devices and the shared memory via the data buffers. Data is transferrable between a transferring data device to a receiving data device by transferring data from the transferring data device to the data buffer corresponding to the transferring data device, from the data buffer corresponding to the transferring data device to the memory bus, from the memory bus to the data buffer corresponding to the receiving data device, and then from the data buffer corresponding to the receiving data device to the receiving data device. A data transfer controller controls the data buffers and the shared memory so that the shared memory does not transfer data onto the memory data bus when, during the transfer of data between the transferring data device and the receiving data device, data is being transferred between the data buffer corresponding to the transferring data device and the data …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.