Package for semiconductor device
US5629559A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1994 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Dec 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a package for mounting of semiconductor device, wherein: PA1 (a) a power layer, a ground layer and a signal layer are laminated via an intermediate layer including an insulating layer, PA1 (b) the power layer and the ground layer are each constituted by an inner lead area, an outer lead area and an electro-conductive area, the inner lead area and the outer lead area being not covered with the intermediate layer and being exposed and the electro-conductive area being interposed between the inner lead area and the outer lead area and covered with the intermediate layer, and PA1 (c) substantially all of the electro-conductive area of each of the power layer and the ground layer is constituted by a planar electro-conductive member. In this package, the self-inductances of the power layer and the ground layer are low and the capacitor formed by these layers has a large capacity; therefore, the power line and ground line noise is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.