Apparatus and method for power reduction in dRAM units
US5629646A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Mar 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a DRAM unit in which the substrate bias voltage is maintained within predetermined limits by a of voltage detectors and a charge pump, a third voltage detector is provided which detects a intermediate substrate bias voltage level that is within the voltage range identified by the pair of voltage detectors. When the third voltage level detects that the intermediate substrate bias voltage has been traversed, the charge pump is activated at a reduced level to drive the substrate bias voltage to recross the intermediate substrate bias voltage level. This technique permits the DRAM unit to operate in a stand-by mode at a lower power level, especially in a standby mode of operation, than when the substrate bias voltage is maintained only by the two voltage limit detectors and a single power level charge pump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.