Self-biased phase-locked loop
US5629650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1996 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Jan 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to the preferred embodiment, a self-biased phase-locked loop is provided that overcomes the limitations of the prior art bias methods and apparatus. In general, a self-biased current controlled semiconductor device, typically a current controlled oscillator, is self biased by the use of a first feedback path, typically provided by a phase-locked loop, where the feedback path provides a control current for controlling the current controlled device. A second feedback path, typically a pair current mirrors, serves as a bias loop having unity gain. The bias loop provides a bias current that is responsive to the control current. This device has the advantage of being self biasing, thus no other biasing circuitry is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.