Graphics display subsystem that allows per pixel double buffer display rejection
US5629723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Sep 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field. The double buffer reject circuit receives a buffer select signal selecting one of the two or more sub-pixel fields of the given pixel to be accessed during a current display frame. In response, the double buffer reject circuit accesses the selected sub-pixel field of the given pixel when the buffer select signal d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.