Electronic arithmetic unit with multiple error detection

US5629945A · kind A · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Peter Sulzberger · Treuchtlingen, DE
• Eberhard Boehl · Reutlingen, DE

Key dates

• Filing date: Feb 14, 1995
• Grant date: May 13, 1997
• Expiry date: Feb 14, 2015

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/104
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An electronic arithmetic unit, such as an ALU, a processor, a controller, or the like, is for the arithmetic gating (combining) of digital operands coded by code bits and supplied via at least one data bus to form data words likewise coded by code bits. The arithmetic gating of the bits of the operands takes place in stages, and in each stage, at least one carry bit is generated. A code-generating unit generates the code bits of the result word from the coded operands while taking into consideration the required operation of the code bits. An additional circuit for duplicated carry generation is assigned to the individual stages. In addition, a testing device is provided for checking the duplicated carry bits for identity. Finally, for each operand, a code checker is provided, which is linked to the individual lines of the at least one data bus via connecting lines, the arithmetic unit and the circuit for duplicated carry generation being connected up between the code checker and the data bus to the connecting lines. In this manner, in addition to faulty operand bits and carry bits, interrupt errors on operand-bit lines can also be detected.