Method for reducing distortion effects on DC off-set voltage and symbol clock tracking in a demodulator
US5629960A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | May 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for reducing the effects of transients on the DC off-set tracking stage and the symbol timing recovery stage in a full duplex or half duplex packet switched data communication system-in which transients occur in the receiver portion of the subscriber when the transmitter portion of a subscriber is keyed ON and OFF is described. The method is dynamically implemented such the DC tracking stage and the symbol timing recovery stage are set in a first "distortion ready" mode during the time that the transmitter is keyed on and off and is set back to a second "normal" mode after the transmission event is over. In the "distortion ready" mode, the symbol timing recovery stage is set in a "freeze" state such that it makes no further timing adjustments to a decision clock that it generates and the DC off-set recovery stage is set to a narrow bandwidth mode such that it does not track large variations in the DC off-set and amplitude in the received signal. As a result, the Tx/on and Tx/off transients do not upset the decision clock synchronization with the forward channel data stream and the DC off-set tracking stage remains stable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.