Method and apparatus for processing using neural network with reduced calculation amount
US5630024A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Jan 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural network circuit and a processing scheme using the neural network circuit in which a synapse calculation for each input value and a corresponding synapse weight of each input value which are expressed by binary bit sequences is carried out by using a sequentially specified bit of the corresponding synapse weight, a summation calculation for sequentially summing synapse calculation results for the input values is carried out to obtain a summation value, a prescribed nonlinear processing is applied to the obtained summation value so as to determine the output value, whether the obtained summation value reached to a saturation region of a transfer characteristic of the prescribed nonlinear processing is judged, the synapse calculation and the summation calculation are controlled to sequentially carry out the synapse calculation from upper bits of the corresponding synapse weight, and to stop the synapse calculation and the summation calculation whenever it is judged that the obtained summation value reached to the saturation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.